1. Field of the Invention
The present invention is generally directed to fabrication of semiconductor devices, and more particularly, to a resultant structure and a process for making an array of transistors and capacitors using double poly complementary metal oxide semiconductor (MOS) technology wherein the thickness of an interpolysilicon oxide layer can be independently adjusted relative to the thickness of gate oxide in a transistor.
2. State of the Art
Double poly MOS technology has been used widely in the design of analog circuits. The advantages of this technology include speed and the virtual elimination of any requirement for standby power.
Methods for fabricating double poly MOS transistors and capacitors are well known in the art. For example, FIGS. 1-5 illustrate typical fabrication steps. FIG. 1 illustrates a semiconductor substrate 10 with an oxide layer formed thereon. The oxide layer includes thick field oxide regions 11 and a thin oxide region 12. A polysilicon layer 14 is formed (e.g., deposited) on substrate 10 over the oxide layer as illustrated in FIG. 2. A photoresist layer 16 is then formed (e.g., coated) on the polysilicon layer 14. The photoresist layer is patterned (e.g., photolithographically) into a mask 16 and used to pattern (i.e., etch) portions of the polysilicon layer in known fashion to form a polysilicon region from layer 14 as illustrated in FIG. 3. The photoresist mask 16 is then removed after which the substrate 10 is dip etched to remove portions of the exposed oxide layer, with entire oxide region 12 being etched as illustrated in FIG. 4. Another oxide layer is then formed (e.g., grown) on substrate 10 to form a gate oxide layer 13 and also an interpolysilicon (i.e., interpoly) oxide layer 18 on top of polysilicon layer 14, as shown in FIG. 5. A second polysilicon layer is formed (e.g., deposited) on substrate 10 and etched to produce a patterned polysilicon layer 20 on top of the gate oxide 13 and a patterned polysilicon top plate 21 on the interpoly oxide layer 18 as shown in FIG. 6. The polysilicon of layer region 14 (representing a bottom plate), the interpoly oxide 18, and the top plate 21 form a capacitor. The polysilicon 20 forms a MOS transistor gate.
Either of the two polysilicon layers (e.g., the layers used to form regions 14 and 21, respectively) formed in the MOS fabrication process described above can be used as a transistor gate. The decision to use the first polysilicon layer or the second polysilicon layer as a transistor gate depends upon the characteristics required for the transistor. There are several disadvantages in selecting the first polysilicon layer as the transistor gate. First, characteristics of the first polysilicon layer can be degraded during the process of growing the interpoly oxide layer on top of the first polysilicon layer. More particularly, the growth of a good interpoly oxide layer requires that the process be conducted at a very high temperature. However, the transistor characteristics are changed by the high temperatures used during the oxide layer formation. Instead of using a high temperature process, a low temperature deposited oxide can be used. However, the quality of low temperature deposited oxide is generally inferior relative to thermally grown oxide. Hence, poor gate and interpoly oxide quality would result.
Using the process of FIGS. 1-6, the interpoly oxide layer 18 is formed at the same time the gate oxide layer 13 is formed. Therefore, the thickness of the interpoly oxide layer cannot be randomly changed without changing the thickness of the gate oxide layer. This seriously limits the porting of existing designs to different MOS processes used in different foundries.